1. Field of the Invention
This invention relates to a method for manufacturing a metal contact on a word line during a manufacturing process of a Dynamic Random Access Memory (DRAM) cell, and more particularly to a method for manufacturing a metal contact on a word line that is capable of isolating a metal from a semiconductor substrate by forming an active area having the injected impurity which is different from that of the semiconductor substrate formed on the semiconductor substrate of both sides of the word line.
2. Information Disclosure Statement
Generally, a N-type polysilicon that contains phosphorous as an impurity is used for a word line of a semiconductor memory device. In such case, the resistance of the polysilicon can be decreased somewhat by injecting the impurity on the semiconductor substrate. However, the resistance is still very high as compared with that of a metal. Accordingly, the signal speed decreases due to the resistance of the word line.
For solving the above mentioned problem, a method of depositing metal layers with a certain interval over the word line is used frequently. However, in a process for manufacturing the metal contact on the word line, the design rule is reduced as a highly integrated DRAM cell is manufactured. Moreover, as the topology is increased, the depth of the contact hole is deepened so that it is difficult to manufacture a highly integrated DRAM cell.
FIG. 1 is a layout illustrating a metal contact on a word line according to the conventional method. FIG. 2 is a cross-sectional view showing a method for manufacturing a metal contact on a word line along II--II of FIG. 1. As shown in FIG. 1 and 2, a metal layer 10 is not directly connected to the word line 15, but the metal layer 10 is connected to a polycide 13 through a metal contact hole after a polysilicon layer 18 and a polycide 19 are sequentially formed and connected to the word line 15.
In the following section, a method for manufacturing the metal contact on the word line 15 according to the conventional method is further explained.
After forming a field oxide layer 13 on a P-well area 11 formed on a silicon substrate (not illustrated), a word line 15 which is comprised of a polysilicon is formed on the field oxide layer 13. Thereafter, a first interpoly oxide layer 16 is deposited over the entire surface and a contact hole for a bit line is formed by etching the predetermined part of the first interpoly oxide layer 16 through a photo etching process utilizing a bit line as a contact mask (not illustrated). After that, a polysilicon layer 18 for a bit line is formed by depositing a polysilicon in a contact hole for a bit line. Then, a polycide layer 19 for a bit line is deposited on the polysilicon layer 18 and a second interpoly oxide layer 17 is deposited over the entire surface. Thereafter, a metal contact hole is formed by etching the predetermined part of the second interpoly oxide layer 17 and a metal layer 10 is formed by depositing a metal in the metal contact hole. Therefore, the metal layer 10 is connected to the polycide layer 19.
In a method for manufacturing a metal contact on a word line according to the conventional technique, since the size of a DRAM cell is reduced as its integrate increases, it is difficult to make a design rule. Also, although the width of the word line of the part where the metal contact is to be formed is decreased, the contact size is restricted due to the reduction of the design rule because the contact must be formed over the word line. In such case, when the word line fails to cover entirely the contact of the bit line, the substrate and metal layer on the word line come into contact so that the leakage of the signal is occurred.
Accordingly, as the design rule is decreased, the contact size must be also decreased. However, as a highly integrated DRAM cell is manufactured, the contact depth is increased and the metal contact cannot effectively be used. To solve these problems, although the contact of the bit line is inserted in the middle to decrease the topology, the contact size of the bit line is limited.